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NanoAmp Solutions, Inc. 670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035 ph: 408-935-7777, FAX: 408-935-7770 www.nanoamp.com
N16D1633LPA
Advance Information
512K x 16 Bits x 2 Banks Low Power Synchronous DRAM
DESCRIPTION
These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Features
* JEDEC standard 3.0V/3.3V power supply. * Auto refresh and self refresh. * All pins are compatible with LVTTL interface. * 4K refresh cycle / 64ms. * Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. * Programmable CAS Latency : 2,3 clocks. * Programmable Driver Strength Control. - Full Strength or 1/2, 1/4 of Full Strength * Deep Power Down Mode * All inputs and outputs referenced to the positive edge of the system clock. * Data mask function by DQM. * Internal dual banks operation. * Burst Read Single Write operation. * Special Function Support. -PASR (Partial Array Self Refresh) -Auto TCSR(Temperature Compensated Self Refresh) * Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge
Table 1: Ordering Information
PART NO. N16D1633LPAZ2-75I N16D1633LPAZ2-10I N16D1633LPAC2-60I N16D1633LPAC2-75I N16D1633LPAC2-10I N16D1633LPAT2-60I N16D1633LPAT2-75I N16D1633LPAT2-10I CLOCK Freq. 133MHz 100MHz 166MHz 133MHz 100MHz 166MHz 133MHz 100MHz -25o C to 85o C 3.0V/3.0V or 3.3V/3.3V Temperature VDD/VDDQ INTERLEAVE PACKAGE 48-Ball Green FBGA 60-Ball Green WBGA 50-Pin Green TSOP II
LVTTL
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
N16D1633LPA
NanoAmp Solutions, Inc. Figure 1: Package Configuration (60-Ball WBGA)
6.4 0.1 1.25 3.9 0.65 Unit [mm]
Advance Information
1 A B C D E F G H J K L M N P R
VSS DQ14 DQ13 DQ12 DQ10 DQ9 DQ8 NC NC NC CKE A11 A8 A6 VSS
2
DQ15 VSSQ VDDQ DQ11 VSSQ VDDQ NC NC UDQM CLK NC A9 A7 A5 A4
3
4
5
6
DQ0 VDDQ VSSQ DQ4 VDDQ VSSQ NC NC LDQM /RAS NC NC A0 A2 A3
7
VDD
A
DQ1 DQ2 DQ3 DQ5 DQ6 DQ7 NC /WE /CAS /CS NC A10 A1
0.65
B C D E F G
10.1 0.1 10.1 0.1
H J K L M N P R
9.1
0.3 0.05 7 6 5 4 3 2 1
VDD
[Top View] [Bottom View]
1.0max
0.23 0.05
Note: 1. All Dimensions in millimeters
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
N16D1633LPA
NanoAmp Solutions, Inc. Figure 2: Package Configuration (48-Ball FBGA)
6.0 0.1 1.125 3.75 0.75 Unit [mm]
Advance Information
1 A B C D E F G H
CLK DQ8 DQ9 VSS VDD DQ14 DQ15 NC
2
/CS NC DQ10 DQ11 DQ12 DQ13 NC A8
3
A0 A3 A5 /RAS NC NC UDQM A9
4
A1 A4 A6 A7 NC NC LDQM A10
5
A2 CKE DQ1 DQ3 DQ4 DQ5 /WE A11
6
/CAS DQ0 DQ2 VDDQ VSSQ DQ6 DQ7 NC A 0.75 B C D E F G H 6 5 4 3 2 1 0.30 0.05
8 0.1 0.23 0.05
1.0max
5.25
[Top View]
[Bottom View]
Note: 1. All Dimensions in millimeters
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
N16D1633LPA
NanoAmp Solutions, Inc. Figure 3: Package Configuration (50-Pin TSOP II) Advance Information
11.76 0.20
VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM /WE /CAS /RAS /CS A11 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 Pin TSOP II
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
GND DQ15 DQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND
0.80 BSC
20.95 0.10
0.49 0.27
1.03 MAX 10.16 0.10
[Top View]
0.80 NOM
1.20 MAX
1.00 0.05
0.17 NOM
0o - 8o 0.15 0.05 0.50 0.10
NOTES: 1. All dimensions in millimeters unless otherwise noted 2. BSC = Basic lead spacing between centers 3. MAX / MIN
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 2: Pin Descriptions
PIN CLK CKE /CS A11 A0~A10 PIN NAME System Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection DESCRIPTIONS The system clock input. All other inputs are registered to the SDRAM on the rising edge of the CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Enable or disable all inputs except CLK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0~RA10 Column Address: CA0~CA7 Auto Precharge : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input/output pin Power supply for internal circuits and input buffers Power Supply for output buffers No Connection
/RAS, /CAS, /WE LDQM/UDQM DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
N16D1633LPA
NanoAmp Solutions, Inc. Figure 4: Functional Block Diagram
EXTENDED MODE REGISTER CLOCK GENERATOR TCSR PASR
Advance Information
CLK CKE
ADDRESS
ROW MODE REGISTER ADDRESS BUFFER & REFRESH COUNTER
BANK B BANK A
ROW DECODER ROW DECODER ROW DECODER
SENSE AMPLIFIER
/CS /RAS /CAS /WE
COLUMN DECODER COLUMN ADDRESS BUFFER & BURST COUNTER
DATA CONTROL CIRCUIT
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
COMMAND DECODER
CONTROL LOGIC
& LATCH CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT BUFFER
DQ
6
N16D1633LPA
NanoAmp Solutions, Inc. Figure 5: Simplified State Diagram
EXTENDED MODE REGISTER SET
EM R S
Advance Information
SELF REFRESH
LF SE SE LF
IT EX
MODE REGISTER SET
MRS IDLE
CK E
D DP IT
REF
CBR REFRESH
CK E
DEEP POWER DOWN
D DP
EX
ROW ACTIVE
T BS
ACT POWER DOWN CKE CKE
BS T
ACTIVE POWER DOWN
E E RG AR CH RE PR TH IT O UT AU ITE W T WR PRE
W AU RIT TO E PR WIT EC H HA RG E
WRITE
READ
WRITE SUSPEND
CKE WRITE CKE
READ
CKE READ CKE
READ SUSPEND
WRITE
WRITE A SUSPEND
CKE WRITE A
ina t ion )
CKE READ A CKE
ge har rec E(P PR
READ A SUSPEND
CKE
POWER ON
PRECHARGE
PRECHARGE
PR E(P rec har g
et
erm
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
n) atio min ter
Automatic Sequence Manual Input
7
N16D1633LPA
NanoAmp Solutions, Inc. Figure 6: Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Advance Information
11 0
10 0
9 WB 0
8 0
7
6
5
4 BT
3
2
1
0
Mode Register (Mx)
CAS Latency
Burst Length
M9 0 1
Write Burst Mode Burst Read and Burst Write Burst Read and Single Write
M6 0 0 0 0 1 1 1 1
M5 0 0 1 1 0 0 1 1
M4 0 1 0 1 0 1 0 1
CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleave
M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
Note: M11(A11) must be sest to "0" to select mode Register (vs. the Extend Mode Register)
Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 3 .
Note : 1. For full-page accesses: y = 256 2. For a burst length of two, A1-A7 select the block-oftwo burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 select the block-offour burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-ofeight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored.
Table 3: Burst Definition
Burst Length Starting Column Address A2 A1 A0 Order of Access Within a Burst Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1. Cn+2, Cn+3, Cn+4... ...Cn-1, Cn... Interleave 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
2
0 4 0 1 1 0 0 0 8 0 1 1 1 1 Full Page 0 0 1 1 0 0 1 1
0 1
0 1 0 1 0 1 0 1 0 1 0 1
N=A0~7 (Location 0-256)
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N16D1633LPA
NanoAmp Solutions, Inc. Figure 7: Extended Mode Register
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Advance Information
11 1
10 0 0
9 0
8 0
7
6 DS
5
4 TCSR
3
2
1 PASR
0 Extended Mode Register (Ex)
E6 0 0 1 1
E5 0 1 0 1
Driver Strength Full Strength 1/2 Strength 1/4 Strength Reserved
E4 0 0 1 1 E2 0 0 0 0 1 1 1 1
E3 0 1 0 1 E1 0 0 1 1 0 0 1 1
Maximum Case Temp. 85 70 45 Auto E0 0 1 0 1 0 1 0 1 All Banks One Bank (A11=0) Reserved Reserved Reserved Half of One Bank (A11=0, Row Address MSB=0) Quarter of One Bank (A11=0, Row Address 2 MSB=0) Reserved Self Refresh Coverage
Note: 1. E11(A11) must be set to "1" to select Extend Mode Register (vs. the base Mode Register)
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
N16D1633LPA
NanoAmp Solutions, Inc. FUNCTIONAL DESCRIPTION
In general, this 16Mb SDRAM (512K x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 8,388,608bit banks is organized as 2,048 rows by 256 columns by 16-bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (A11 select the bank, A0-A10 select the row). The address bits (A11 select the bank, A0-A7 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Advance Information
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command has been issued. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation.
REGISTER DEFINITION
Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
EXTENDED MODE REGISTER
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (A11=1) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with E7 through E10 set to "0". The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before before initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N16D1633LPA
NanoAmp Solutions, Inc. Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
Advance Information
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating /CS, /RAS and deasserting /CAS, /WE at the positive edge of the clock. The value on the A11 selects the bank, and the value on the A0-A10 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating /CS, /CAS, and deasserting /WE, /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating /CS, /CAS, /WE and deasserting /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
N16D1633LPA
NanoAmp Solutions, Inc. CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Advance Information
Figure 8: CAS Latency
T0 CLK T1 T2 T3
COMMAND
READ
NOP tLZ
NOP tOH Dout
DQ tAC CAS Latency=2
T0 CLK
T1
T2
T3
T4
COMMAND
READ
NOP
NOP tLZ
NOP tOH Dout
DQ tAC CAS Latency=3
DON'T CARE UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
12
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 4: Command Truth Table
COMMAND Command Inhibit (NOP) No Operation (NOP) Mode Register Set Extended Mode Register Set Active (select bank and activate row) Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge Selected Bank Burst stop Auto Refresh Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Down Exit Clock Suspend Entry Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit Note : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previoys clock edge. H: High Level, L: Low Level, X: Don't Care, V: Valid 2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A mimum of two NOP commands must be provided during tXSR period. 3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. DQM "L" means the data Write/Ouput Enable and "H" means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK. 6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is assigned to the Deep Power Down function. CKEn-1 H H H H H H H H H H H H H H L H L H L H L CKEn X X X X X X X X X X X H H L H L H L H L H L H X CS H L L L L L L L L L L L L L H L H L H L H L RAS X H L L L H H H H L L H L L X H X H X H X V X H L CAS X H L L H L L L L H H H L L X H X H X H X V WE X H L L H H H L L L L L H H X H X H X H X V DQM X X X X X L/H L/H L/H L/H X X X X X X X X X X X X ADDR X X OP-CODE OP-CODE Bank/Row Bank/Col Bank/Col Bank/Col Bank/Col X Bank X X X X X X X X X X 6 3 3 2 L H L H H L 5 5 5 5 4 4 A10 Note
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 5: Function Truth Table
Current State Command /CS L L L
IDLE
/RAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X
/CAS L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X
/WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X
A11 OP CODE X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X
A0-A10
Description Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect
Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the Specific Bank and Row ILLEGAL ILLEGAL NOP NOP or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : Optional AP(A10 = H) Start Read: Optional AP(A10 = H) NOP NOP ILLEGAL ILLEGAL Termination Burst : Start the Precharge ILLEGAL Termination Burst: Start Write(AP) Termination Burst: Start Read(AP) Continue the Burst Continue the Burst ILLEGAL ILLEGAL Termination Burst : Start the Precharge ILLEGAL Termination Burst: Start Write(AP) Termination Burst: Start Read(AP) Continue the Burst Continue the Burst
Note 14 5
L L L L H L L L L
Row Addr Col Addr/A10 Col Addr/A10 X X X X Row Addr Col Addr/A10 Col Addr/A10 X X X X Row Addr Col Addr/A10 Col Addr/A10 X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
4 4 3 3 13,14 13 7 4 6 6
OP CODE
ROW ACTIVE
L L L H L L L L
OP CODE
13,14 13
4 8,9 8
READ
L L L H L L L L
OP CODE
13,14 13
4 8,9 8
WRITE
L L L H
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
14
N16D1633LPA
NanoAmp Solutions, Inc. Table 5: Function Truth Table
Current State Command /CS L L
READ with AUTO PRECHARGE
Advance Information
/RAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X
/CAS L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X
/WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X
A11 OP CODE X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X
A0-A10
Description Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Action
Note 13,14 13 4,12 4,12 12 12
L L L L L H L L L L L L L H L L L
Row Addr Col Addr/A10 Col Addr/A10 X X X X Row Addr Col Addr/A10 Col Addr/A10 X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation: Bank(s) Idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) Idle after tRP No Operation: Bank(s) Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Activated after tRCD No Operation: Row Activated after tRCD 13,14 13 4,12 4, 11, 12 4,12 4,12 4,12 4,12 4,12 13,14 13 13,14 13 4,12 4,12 12 12
OP CODE
WRITE with AUTO PRECHARGE
OP CODE
PRECHARGING
L L L L H L L L L
OP CODE X BA BA BA BA X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
ROW ACTIVATING
L L L H
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
15
N16D1633LPA
NanoAmp Solutions, Inc. Table 5: Function Truth Table
Current State Command /CS L L L L
WRITE RECOVERING
Advance Information
/RAS L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X
/CAS L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X
/WE L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X
A11 OP CODE X BA BA BA BA X X X X
A0-A10
Description Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active Write/Write AP Read/Read AP NOP Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Action
Note 13,14 13 4,13 4,12
Row Addr Col Addr/A10 Col Addr/A10 X X
L L L H L L L L L L L H L L L L L L L H L L L L
Start Write : Optional AP(A10 = H) Start Write : Optional AP(A10 = H) No Operation : Row Active after tDPL No Operation : Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Precharge after tDPL No Operation : Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Idle after tRC No Operation : Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Idle after 2 Clock Cycle No Operation : Idle after 2 Clock Cycle 13,14 13 13 13 13 13 13,14 13 13 13 13 13 13,14 13 4,13 4,12 4,12 4,9, 12 9
OP CODE X BA BA BA BA X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
Write Recovering with Auto Precharge
OP CODE X BA BA BA BA X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
REFRES HING
OP CODE X BA BA BA BA X X X X Row Addr Col Addr/A10 Col Addr/A10 X X
Mode Register Accessing
L L L H
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
16
N16D1633LPA
NanoAmp Solutions, Inc.
Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except A11.
Advance Information
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
17
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 6: CKE Truth Table
Current State CKE Prev Cycle H L
Self Refresh
Command /CS X H L L L L X X H L L /RAS X X H H H L X X X H L X X /CAS X X H H L X X X X H X L X X X X X X X H L L X X H L L X X X X X /WE X X H L X X X X X H X X L X X X X X X X H L X X X H L X X X X X X X X X X X X Op-Code X X X X X X X Op-Code A11 X X X X X X X X X X X X X X X X X A0-A10 X X X X X X X X X X X X X X X X X Maintain Power Down Mode INVALID Deep Power Down Mode Set Maintain Deep Power Down Mode Refer to the Idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to Operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 5 5 4 4 4 5 4 4 4 2 6 ILLEGAL 3 Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode Exit, All Banks Idle 2 3 Note 2 3 3 3 3 3
Current Cycle X H H H H H L X H
L L L L L H L
Power Down
L
H
L H
Deep Power Down
L X H L H H H H H L L L L L X H L H L
X X X X H L L L L H L L L L X X X X X
X X X X X H L L L X H L L L X X X X X
L L H H H H H
All Bank Idle
H H H H H L H
Any State other than listed above
H L L
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
18
N16D1633LPA
NanoAmp Solutions, Inc.
Note : 1. H: Logic High, L: Logic Low, X: Don't care 2. For the given current state CKE must be low in the previous cycle. 3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 4. The address inputs depend on the command that is issued. 5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 100usec.
Advance Information
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
19
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 7: ABSOLUTE MAXIMUM RATING
PARAMETER Ambient Temperature (Industrial) Ambient Temperature (Commerical) Storage Temperature Voltage on Any Pin Relative to VSS Voltage on VDD Relative to VSS Short Circuit Output Current Power Dissipation
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
SYMBOL TA TSTG VIN, VOUT VDD, VDDQ IOS PD
RATING -25 ~ 85 0 ~ 70 -55~150 -1.0~4.6 -1.0~4.6 50 1
UNIT
C C
V V mA W
Table 8: Capacitance (TA = 25C, f = 1MHz, VDD = 3.0V or 3.3V)
PARAMETER Input Capacitance Data Input / Output Capacitance PIN CLK A0~A11, CKE, /CS /RAS, /CAS, /WE, L(U)DQM DQ0~DQ15 SYMBOL Cl1 Cl2 CIO MIN 2 2 3 MAX 4 4 5 UNIT pF pF pF
Table 9: DC CHARACTERISTIC & OPERATION CONDITION (TA = -25 to 85C)
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output Logic High Current Output Logic Low Current Input Leakage Current Output Leakage Current
Note : 1. VDDQ must not exceed the level of VDD 2. VIH(max) = 5.3V AC. The overshoot voltage duration is 3ns 3. VIL(min) = -2.0V AC. The overshoot voltage duration is 3ns. 4. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs 5. DOUT is disabled, 0V VOUT VDDQ.
SYMBOL VDD VDDQ VIH VIL VOH VOL ILI ILO
MIN 2.7 2.7 2.2 -0.3 2.4 --1 -1.5
TYP 3.0 3.0 -0 -----
MAX 3.6 3.6 VDDQ+0.3 0.5 -0.4 1 1.5
UNIT V V V V V V A A
NOTE 1 2 3 IOH = -0.1mA IOL = +0.1mA 4 5
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
20
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 10: AC OPERATNG CONDITION (TA = -25 to 85C, VDD=3.0V or 3.3V 0.3V, VSS = 0V)
PARAMETER AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement SYMBOL VIH / VIL Vtrip tR / tF Voutref CL TYP 2.4/0.4 0.5 x VDDQ 1/1 0.5 x VDDQ 30 UNIT V V ns V pF
VDDQ 1200 Output 870 30pF Output Z0=50
VTT=0.5 x VDDQ
50
30pF
DC Output Load Circuit
AC Output Load Circuit
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
21
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 11: DC CHARACTERISTIC (DC Operating Conditions Unless Otherwise Noted)
PARAMETER SYM TEST CONDITION Burst Length=1, One Bank Active tRC tRC (min) IOL=0mA CKE VIL (max), tCK=10ns CKE & CLK VIL(max), tCK= CKEVIH (min), /CSVIH(min), tCK=10ns Input Signal are changed one time during 2clks. CKEVIH (min), /CSVIH(min)
ICC2NS ICC3P ICC3PS
SPEED 60
UNIT NOTE
75 30 60 60
10 mA uA uA 1 ---
Operating Current Precharge Standby Current in Power Down Mode
ICC1 ICC2P ICC2PS
ICC2N
6
mA
--
Precharge Standby Current in Non Power Down Mode
tCK= Input signals are stable CKEVIL(max), tCK=10ns CKE & CLK VIL(max), tCK= CKEVIH(min), /CSVIH(min), tCK=10ns Input Signals are changed one time during 2clks CKEVIH(min), CLK VIL(max) tCK= Input Signals are stable tCKtCK(min), IOL=0mA, Page Burst All Banks Activated, tCCD = 1clk tRC tRFC (min) All banks active 55
1 0.5 0.5
mA mA mA
----
Active Standby Current in PowerDown Mode
ICC3N
12
mA
--
Active Standby Current in Non Power-Down Mode
ICC3NS
6
mA
--
Operating Current (Burst Mode) Auto Refresh Current PASR Self Refresh Current 2Bank 1Bank TCSR 45~85C -25~45C 45~85C -25~45C
ICC4 ICC5
45 30
35
mA mA
1 2
85 ~ 100
ICC6
CKE 0.2V
70 ~ 85 80 ~ 95 65 ~ 80
uA
Deep Power Down Mode Current Note: 1. Measured with outputs open. 2. Refresh period is 64ms.
ICC7
20
uA
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
22
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information
Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted)
PARAMETER
CL=3 CL=2 CL=3 CL=2
SYM
tCK3 tCK2 tAC3 tAC2 tCH tCL tCKS tCKH tCMS tCMH tAS tAH tDS tDH
-60 MIN 6.0 10 MAX 1000 5.5 8 2.5 2.5 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 5.5 8 1.0 2.5 1.8 42 18 60 12 18 1 0 12 30 2 0 2 3 2 1 1 1 1 1 100K 1.0 2.5 1.8 45 22.5 67.5 15 22.5 1 0 15 37.5 2 0 2 3 2 1 1 1 1 1 2.5 2.5 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 MIN 7.5 10
-75 MAX 1000 6 8 2.5 2.5 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 6 8 1.0 2.5 1.8 100K 40 20 60 20 20 1 0 20 40 2 0 2 3 2 1 1 1 1 1 MIN 10 10
-10 MAX 1000 8 8
UNIT
NOTE
CLK Cycle Time Access time from CLK (pos. edge) CLK High-Level Width CLK Low-Level Width CKE Setup Time CKE Hold Time
1 2 3 3
/CS, /RAS, /CAS, /WE, DQM Setup Time /CS, /RAS, /CAS, /WE, DQM Hold TIme Address Setup Time Address Hold Time Data-In Setup Time Data-In Hold Time Data-Out High-Impedance Time from CLK (pos.edge) Data-Out Low-Impedance Time Data-Out Hold Time (load) Data-Out Hold Time (no load) ACTIVE to PRECHARGE command PRECHARGE command period ACTIVE bank a to ACTIVE bank a command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay READ/WRITE command to READ/WRITE command WRITE command to input data delay Data-in to PRECHARGE command Data-in to ACTIVE command DQM to data high-impedance during READs DQM to data mask during WRITES LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode Self Refresh Exit Time
CL=3 CL=2 CL=3 CL=2
ns 8 8
tHZ3 tHZ2 tLZ tOH tOHN tRAS tRP tRC
4
100K
5
tRRD tRCD tCCD tDWD tDPL tDAL tDQZ tDQM tMRD tROH3 tROH2 tBDL tCDL
CLK CLK ns
6 6 7 7 6 6 8 6
CLK
6 6 9 9 10
tCKED
tPED tSRE
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
23
N16D1633LPA
NanoAmp Solutions, Inc. Advance Information Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted)
PARAMETER Refresh Period (4,096 rows) AUTO REFRESH period Exit SELF REFRESH to ACTIVE command Transition time SYM
tREF tRFC tXSR tT
-60 MIN 66 66 0.5 1.2 MAX 64 67.5 67.5 0.5 MIN
-75 MAX 64 70 70 1.2 0.5 MIN
-10 MAX 64
UNIT ms
NOTE
5 ns 1.2 5
Note: 1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to reduce the data rate. 2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. 3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 5. Parameter guaranteed by design. A. Target values listed with alternative values in parentheses. B. tRFC must be less than or equal to tRC+1CLK tXSR must be less than or equal to tRC+1CLK 6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate 8. JEDEC and PC100 specify three clocks. 9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate. 10. A new command can be given tRC after self refresh exit.
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
24
N16D1633LPA
NanoAmp Solutions, Inc. SPECIAL OPERATION FOR LOW POWER CONSUMPTION
TEMPERATURE COMPENSATED SELF REFRESH Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Setting E4 and E3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. PARTIAL ARRAY SELF REFRESH For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One Bank;bank a. WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost. DEEP POWER DOWN Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high.
Advance Information
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
25
N16D1633LPA
NanoAmp Solutions, Inc. Figure 9: Deep Power Down Mode Entry
CLK CKE /CS /RAS tRP Precharge if needed Deep Power Down Entry
Advance Information
Figure 10: Deep Power Down Mode Exit
CLK CKE /CS /RAS /CAS /WE 100 s Deep Power Down Exit tRP Auto Refresh Auto Refresh tRFC Mode Register Set New Command Extended Mode Register Set
All Banks Precharge
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
26
N16D1633LPA
NanoAmp Solutions, Inc. Ordering Information Advance Information
N
16
D 16 33 LP A
XX - XX X
Temperature
NanoAmp Solutions
C = Commercial (0-70C) I = Industrial (-25 to 85) Speed 60 = 6.0ns (166MHz) 75 = 7.5ns (133MHz) 10 = 10ns (100MHz) Package Z2 = Green 48FBGA (RoHS Compliant) C2 = Green 60WBGA (RoHS Compliant) T2 = Green 50 TSOP2 (RoHS Compliant) Generation A = 1ST Generation Features LP = Low Power SDRAM
Density 16= 16Mb Product Type D = SDRAM Data I/O Width 16 = 16 I/O Power Supply 33 = 3.0/3.3V
Revision History
Revision
A B C D E
Date
November 18 2004 November 30 2004 December 15 2004 February 16, 2005 February 23, 2005 Initial ADVANCE Release
Change Description
Changed Refresh Time to 4K / 64ms General Update. Added BGA package option Changed Driver Strength control EMRS Table Changed Pin Ordering (Page 2) Changed Pin Name BA to A11 Removed 2/3 Reg Drive Strength (Page 1) Updated Extend Mode Register Diagram (Page 8) Modifed Pin Name Description (Page 10) Updated Command Truth Table (Burst Stop). Changed CKEn "X" to "H" (Page 12) Updated Partial Array Description. Changed Bank 0 to Bank a (Page 24) Updated Mode Register and Extended Mode Register Diagram (Page 7, 8, 9, 24) Fixed Typo in Table 3 (Page 7) Updated Footnote #14(Page 16) Deleted tSRE from AC Timing Table and Footnote #10 (Page 22, 23) Changed 48FBGA and 60WBGA package thickness to 1.0mm Max Added Pb-Free ordering option for 48FBGA package and 60WBGA package Changed 48FBGA ordering option to Green instead of Pb-Free Added 50-pin TSOP II package option Updated AC/DC characteristics and added green TSOP II Designated green package to be RoHS Compliant
F
March 1, 2005
G
March 3, 2005
H I J K L
May 3, 2005 May 11, 2005 July 19, 2005 August 15, 2005 January 2006
(c) 2004-2005 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
27

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